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By G. Russell, I. Sayers

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73 V DD. 31. Explain any discrepancies. 7. Consider a two stage design: OR-OR-AND-INVERT + HIskew INV. G = 2 * 5/6 = 5/3. P = 4 + 5/6 = 29/6. 8. 27. 4 τ. 27 = 79. 36 One design is: Dynamic NAND2 - HI skew INV - Dynamic NAND2 - HI skew INV. G = 1 * (5/6) * 1 * (5/6) = 25/36. 3. 3. 7. 1 τ. 38 The static designs with and without complex AAOI gates use 28 and 40 transistors, respectively. The nonrestoring transmission gate design uses 16 transistors, though adding inverters on the inputs would raise that to 24 and make the mux restoring but inverting.

11 (a) 700 ps; (b) 825 ps; (c) 1200 ps. The transparent latches are skew-tolerant and moderate amounts of skew do not slow the cycle time. 15 t pd = 500 - 2(40) = 420 ps. 16 t pd = 500 - 2(40 + 50) = 320 ps. 17 t pd = 500 ps. Skew-tolerant domino with no latches has no sequencing overhead. 18 t pd = 500 ps. The path can tolerate moderate amounts of skew without degradation. 19 t borrow = 125 ps - 50 ps - thold = 75 ps - thold. 25)*500 - 50 ps - t hold= 150 ps - t hold. 25 If the output goes metastable near V DD/2, the flip-flop will indeed produce a good high output.

E. set flip flops to zero) Place signature analyzer in “analyze” mode Cycle LFSR through a “large” number of vectors – can be exhaustive. Shift signature analyzer out and observe syndrome – check whether it matches the simulated value. If it does your circuit is OK, if not, it’s faulty. 14 The data input, address and control (read/write controls and clocks) are muxed with test generators. The test structure for the address can be a counter. The data generator can be a simple logic structure that generates “all 0’s”, “all 1’s” and “alternating 1’s and 0’s”.

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Advanced Simulation and Test Methodols for VLSI Design by G. Russell, I. Sayers


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