By Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund
The promising excessive information expense instant functions at millimeter wave frequencies mostly and 60 GHz specifically have received a lot recognition lately. even though, demanding situations regarding circuit, structure and measurements in the course of mm-wave CMOS IC layout need to be conquer prior to they could turn into achievable for mass market.60-GHz CMOS Phase-Locked Loops concentrating on phase-locked loops for 60 GHz instant transceivers elaborates those demanding situations and proposes recommendations for them. The process point layout to circuit point implementation of the whole PLL, besides separate implementations of person parts reminiscent of voltage managed oscillators, injection locked frequency dividers and their combos, are incorporated. in addition, to fulfill a few transceiver topologies concurrently, flexibility is brought within the PLL structure by utilizing new dual-mode ILFDs and switchable VCOs, whereas reusing the low frequency parts on the related time.
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Extra resources for 60-GHz CMOS Phase-Locked Loops
16) closely match. Therefore, the overall calculations are unaffected and the loop filter does not require different resistance and capacitance for the two front-ends. This re-usability of the area consuming LPF saves considerable silicon area. 2 pF. 74 pF is calculated using the capacitance ratio term, m. 4. 5 System Simulations PLL based frequency synthesizers consist of components operating at vastly different frequencies. The VCO and prescaler, operating at the highest frequencies, require a high numerical sampling rate in the simulations whereas the low frequency components like PFD have large time constants.
Therefore, a number of different simulation and extraction tools are utilized to accomplish the task. A typical IC design flow is shown in Fig. 2. It is to be noted, as will be explained shortly, that the steps inside the dashed box are more critical in a mm-wave design flow as compared to a low frequency design. In case the post-layout simulations, which usually include RC extraction from one tool and inductance extraction from EM-solvers, do not meet the required specifications, the layout has to be modified and subsequently the extraction has to be repeated.
Therefore, small discontinuities (patterns) in the ground shield are introduced to reduce these eddy current loops to smaller area thereby lowering the cancellation effect. In addition, there is less magnetic field penetration into the substrate resulting in reduction of substrate losses. A few examples of patterned ground shields are shown in Fig. 6a–c. The drawback of the shield method is the possible reduction of self-resonance frequency (FSR) of the inductor caused by the increased capacitance.
60-GHz CMOS Phase-Locked Loops by Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund